In semiconductor production, it is known to produce structures on a wafer surface by means of photolithographic processes. By way of example, structures are projected onto a photosensitive layer by means of a photolithographic stepper or scanner. Alongside other structures, gate regions of transistor gates of integrated circuits are regularly produced by means of a photolithographic process on the basis of the patterning of a polysilicon layer on the surface of a dielectric, for example, silicon oxide or silicon oxynitride. The minimum achievable sizes for line structures and equally the minimum achievable distances between adjacent line structures are limited by the parameters of a photolithographic system. One limiting factor is, for example, the prevailing wavelength for the illumination for a light source during the projection of the structures onto the surface of a substrate to be patterned. In addition, mechanical tolerances and the aperture of the optical path are limiting factors. For an existing photolithographic system, the minimum achievable feature size is a fixed parameter designated as the critical dimension. A critical gap dimension is regularly approximately of the order of magnitude of a critical line dimension. Semiconductor processes are often specified exactly according to these parameters, e.g. 200 nm technology node or 90 nm technology node.
The transition to a technology with a smaller critical dimension is very expensive, for which reason attempts are made to be able to achieve the smallest possible dimensions in the existing technology.
For the properties, for example, a transistor, it may be advantageous to achieve a gate channel length that is as small as possible. With a smaller gate channel length it is possible to reduce the necessary supply voltage, as a result of which the power consumption decreases. Furthermore, it is possible to increase the clock rate.
In the attempt to achieve smaller structures, however, the disadvantage arises when the distance between the structures increases, that is the gap width between the structures increases. In specific applications, there is a desire precisely for a distance that is as small as possible between gate structures, for example, the case of CCDs (Charge coupled devices). In order to achieve this, the prior art discloses using a technology in which a double gate patterning process is employed. The overlapping of two gate structures makes it possible to produce a minimum distance between the gates.
In this process, however, the performance of standard transistors is detrimentally affected on account of a required high-temperature oxidation process for producing an oxide spacer between two polysilicon layers.
Furthermore, it is possible to use an improved photolithographic process which enables smaller structures to be realized. However, this is associated with a significant additional outlay in respect of costs.